1. Field of the Invention
This disclosure relates to a semiconductor memory device, and more particularly, to a fin Field Effect Transistor (FET) having a fin type active region.
2. Description of the Related Art
As the trend to achieve semiconductor memory devices having low power, high efficiency, and high speed characteristics continues, a design rule is continuously reduced to integrate more semiconductor memory devices into a semiconductor chip of limited size. In particular, in a highly integrated DRAM (Dynamic Random Access Memory) device, a design rule may be 100 nm, thus an interval from a gate is gradually reduced, generating a short channel effect and increasing the channel doping density of transistors constituting a memory cell. When the channel doping density of the transistors increases to a level of 1013 ion atoms/cm3, a junction leakage current of a storage node lower part of a capacitor may increase, lowering the refresh characteristics.
To solve these problems, fin FETs have been manufactured by forming an active region of fin type on a semiconductor substrate and then by forming a gate electrode on the fin active region. The fin FET may employ an SOI (Silicon On Insulator) silicon substrate an interlayer insulation layer is formed in a lower part of semiconductor substrate, or a bulk silicon substrate. A fin FET that employs the SOI silicon substrate is disclosed in U.S. Pat. No. 6,525,403 entitled “SEMICONDUCTOR DEVICE HAVING MIS FIELD EFFECT TRANSISTORS OR THREE-DIMENSIONAL STRUCTURE”. A method of forming a fin FET on a bulk silicon substrate is disclosed in U.S. Pat. No. 6,642,090 with the title of “FIN FET DEVICES FROM BULK SEMICONDUTOR AND METHOD FOR FORMING”.
A fin FET of the type described above may use an entire face of a projected-portion as a channel. Thus, the channel length is sufficient to prevent or substantially reduce the short channel effect and improve the swing characteristics of the transistor. However, when the fin active region is less than 100 nm, the threshold voltage is difficult to control compared to a planar-type transistor or a recess-type transistor. Furthermore, a leakage current is generated in an off state of the fin FET, and a gate induced drain leakage (GIDL) and a junction leakage current are not distinctly improved compared to the planar type transistor and the recess type transistor.
Embodiments of the invention address these and other disadvantages of the conventional art.